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參數(shù)資料
| 型號： | EPCS4SI8N |
| 廠商： | Altera |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 4MBIT 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | EPCS |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 4Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1379-5 EPCS4SI8N-ND |
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EPCS Device Memory Access
Page 15
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Write Enable Operation
The write enable operation code is b'0000 0110, and it lists the MSB first. The write
enable operation sets the write enable latch bit, which is bit 1 in the status register.
Always set the write enable latch bit before write bytes, write status, erase bulk, and
erase sector operations. Figure 5 shows the instruction sequence of the write enable
operation.
Write Disable Operation
The write disable operation code is b'0000 0100 and it lists the MSB first. The write
disable operation resets the write enable latch bit, which is bit 1 in the status register.
To prevent the memory from being written unintentionally, the write enable latch bit
is automatically reset when implementing the write disable operation, and under the
following conditions:
■
Power up
■
Write bytes operation completion
■
Write status operation completion
■
Erase bulk operation completion
■
Erase sector operation completion
Erase sector
1101 1000
30
0
25
Read device
identification (5)
1001 1111
0
2
1 to infinite (2)
25
Notes to Table 8:
(1) List MSB first and LSB last.
(2) The status register, data, or silicon ID is read out at least once on the DATA pin and is continuously read out until the nCS pin is driven high.
(3) A write bytes operation requires at least one data byte on the DATA pin. If more than 256 bytes are sent to the device, only the last 256 bytes
are written to the memory.
(4) The read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64 devices.
(5) The read device identification operation is available only for EPCS128 devices.
Table 8. EPCS Devices Operation Codes
Operation
Operation Code (1)
Address Bytes
Dummy Bytes
Data Bytes
DCLK fMAX
(MHz)
Figure 5. Write Enable Operation Timing Diagram
nCS
DCLK
ASDI
DATA
01234567
Operation Code
High Impedance
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPCS4SI8N | 制造商:Altera Corporation 功能描述:SEMICONDUCTOR ((NW)) |
| EPCS64 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Serial Configuration Devices |
| EPCS64SI16N | 功能描述:FPGA-配置存儲(chǔ)器 IC - Ser. Config Mem Flash 64Mb 40 MHz RoHS:否 制造商:Altera Corporation 存儲(chǔ)類型:Flash 存儲(chǔ)容量:1.6 Mbit 工作頻率:10 MHz 電源電壓-最大:5.25 V 電源電壓-最小:3 V 電源電流:50 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-20 |
| EPCSC2.5T | 功能描述:接線端子工具和配件 End Plate RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
| EPCSC2.5T1-2 | 功能描述:接線端子工具和配件 End Plate RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Tools & Accessories 類型:End Bracket |
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