Stratix
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S90F1020C3
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 54/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 90K 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 6
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 4548
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 90960
RAM 浣嶇附瑷堬細 4520488
杓稿叆/杓稿嚭鏁�(sh霉)锛� 758
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1917
EP2S90F1020C3-ND
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�绗�756闋�绗�757闋�绗�758闋�绗�759闋�绗�760闋�绗�761闋�绗�762闋�绗�763闋�绗�764闋�绗�765闋�绗�766闋�绗�767闋�绗�768闋�
Altera Corporation
5鈥�1
April 2011
5. DC & Switching
Characteristics
Operating
Conditions
Stratix II devices are offered in both commercial and industrial grades.
Industrial devices are offered in -4 speed grades and commercial devices
are offered in -3 (fastest), -4, -5 speed grades.
Tables 5鈥�1 through 5鈥�32 provide information about absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Stratix II devices.
Absolute Maximum Ratings
Table 5鈥�1 contains the absolute maximum ratings for the Stratix II device
family.
Table 5鈥�1. Stratix II Device Absolute Maximum Ratings
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCINT
Supply voltage
With respect to ground
鈥�0.5
1.8
V
VCCIO
Supply voltage
With respect to ground
鈥�0.5
4.6
V
VCCPD
Supply voltage
With respect to ground
鈥�0.5
4.6
V
VCCA
Analog power supply for
PLLs
With respect to ground
鈥�0.5
1.8
V
VCCD
Digital power supply for PLLs With respect to ground
鈥�0.5
1.8
V
VI
DC input voltage (4)
鈥�0.5
4.6
V
IOUT
DC output current, per pin
鈥�25
40
mA
TSTG
Storage temperature
No bias
鈥�65
150
掳C
TJ
Junction temperature
BGA packages under bias
鈥�55
125
掳C
(1)
See the Operating Requirements for Altera Devices Data Sheet.
(2)
Conditions beyond those listed in Table 5鈥�1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3)
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4)
During transitions, the inputs may overshoot to the voltage shown in Table 5鈥�2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to 鈥�2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
SII51005-4.5
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EP2S90F1020C4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1020C4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1020C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256