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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S90F1020C3
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 465/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 90K 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 6
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 4548
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 90960
RAM 浣嶇附瑷堬細 4520488
杓稿叆/杓稿嚭鏁�(sh霉)锛� 758
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1917
EP2S90F1020C3-ND
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Altera Corporation
6鈥�1
January 2008
6. DSP Blocks in Stratix II and
Stratix II GX Devices
Introduction
Stratix II and Stratix II GX devices have dedicated digital signal
processing (DSP) blocks optimized for DSP applications requiring high
data throughput. These DSP blocks combined with the flexibility of
programmable logic devices (PLDs), provide you with the ability to
implement various high performance DSP functions easily. Complex
systems such as CDMA2000, voice over Internet protocol (VoIP), high-
definition television (HDTV) require high performance DSP blocks to
process data. These system designs typically use DSP blocks as finite
impulse response (FIR) filters, complex FIR filters, fast Fourier transform
(FFT) functions, discrete cosine transform (DCT) functions, and
correlators.
Stratix II and Stratix II GX DSP blocks consist of a combination of
dedicated blocks that perform multiplication, addition, subtraction,
accumulation, and summation operations. You can configure these blocks
to implement arithmetic functions like multipliers, multiply-adders and
multiply-accumulators which are necessary for most DSP functions.
Along with the DSP blocks, the TriMatrixTM memory structures in
Stratix II and Stratix II GX devices also support various soft multiplier
implementations. The combination of soft multipliers and dedicated DSP
blocks increases the number of multipliers available in Stratix II and
Stratix II GX devices and provides you with a wide variety of
implementation options and flexibility when designing your systems.
f
See the Stratix II Device Family Data Sheet in volume 1 of the Stratix II
Device Handbook or the Stratix II GX Device Family Data Sheet in volume 1
of the Stratix II GX Device Handbook for more information on Stratix II
and Stratix II GX devices, respectively.
DSP Block
Overview
Each Stratix II and Stratix II GX device has two to four columns of DSP
blocks that efficiently implement multiplication, multiply-accumulate
(MAC) and multiply-add functions. Figure 6鈥�1 shows the arrangement of
one of the DSP block columns with the surrounding LABs. Each DSP
block can be configured to support:
鈻�
Eight 9 脳 9-bit multipliers
鈻�
Four 18 脳 18-bit multipliers
鈻�
One 36 脳 36-bit multiplier
SII52006-2.2
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
EP4SGX110HF35I4 IC STRATIX IV FPGA 110K 1152FBGA
ACM36DTMT-S664 CONN EDGECARD 72POS R/A .156
EP4SGX110DF29I3 IC STRATIX IV FPGA 110K 780FBGA
EP4SGX110DF29C2X IC STRATIX IV FPGA 110K 780FBGA
ACM36DTBT-S664 CONN EDGECARD 72POS R/A .156
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EP2S90F1020C4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1020C4N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S90F1020C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 4548 LABs 758 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256