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鍙冩暩璩囨枡
鍨嬭櫉锛� EP2S60F672C5N
寤犲晢锛� Altera
鏂囦欢闋佹暩锛� 50/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 672-FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 10
绯诲垪锛� Stratix® II
LAB/CLB鏁革細 3022
閭忚集鍏冧欢/鍠厓鏁革細 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁革細 492
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 672-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 672-BGA锛�27x27锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1914
EP2S60F672C5N-ND
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Altera Corporation
4鈥�3
May 2007
Stratix II Device Handbook, Volume 1
Hot Socketing & Power-On Reset
IIOPIN is the current at any user I/O pin on the device. This specification
takes into account the pin capacitance, but not board trace and external
loading capacitance. Additional capacitance for trace, connector, and
loading needs must be considered separately. For the AC specification,
the peak current duration is 10 ns or less because of power-up transients.
For more information, refer to the Hot-Socketing & Power-Sequencing
Feature & Testing for Altera Devices white paper.
A possible concern regarding hot-socketing is the potential for latch-up.
Latch-up can occur when electrical subsystems are hot-socketed into an
active system. During hot-socketing, the signal pins may be connected
and driven by the active system before the power supply can provide
current to the device's VCC and ground planes. This condition can lead to
latch-up and cause a low-impedance path from VCC to ground within the
device. As a result, the device extends a large amount of current, possibly
causing electrical damage. Nevertheless, Stratix II devices are immune to
latch-up when hot-socketing.
Hot Socketing
Feature
Implementation
in Stratix II
Devices
The hot socketing feature turns off the output buffer during the power-up
event (either VCCINT, VCCIO, or VCCPD supplies) or power down. The hot-
socket circuit will generate an internal HOTSCKT signal when either
VCCINT, VCCIO, or VCCPD is below threshold voltage. The HOTSCKT signal
will cut off the output buffer to make sure that no DC current (except for
weak pull up leaking) leaks through the pin. When VCC ramps up very
slowly, VCC is still relatively low even after the POR signal is released and
the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins
fail to respond, as the output buffer can not flip from the state set by the
hot socketing circuit at this low VCC voltage. Therefore, the hot socketing
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. It is expected behavior for
these pins to drive out during power-up and power-down sequences.
Each I/O pin has the following circuitry shown in Figure 4鈥�1.
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TACL106M003RTA CAP TANT 10UF 3V 20% 0603
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PCA9633DP2,118 IC LED DRIVER RGBA 10-TSSOP
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