Altera Corporation
1–91
July 2009
Stratix II Device Handbook, Volume 2
PLLs in Stratix II and Stratix II GX Devices
The PLL can remain locked independent of the clkena signals since the
loop-related counters are not affected. This feature is useful for
applications that require a low power or sleep mode. Upon re-enabling,
the PLL does not need a resynchronization or relock period. The clkena
signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during resynchronization.
Conclusion
Stratix II and Stratix II GX device enhanced and fast PLLs provide you
with complete control of device clocks and system timing. These PLLs are
capable of offering flexible system-level clock management that was
previously only available in discrete PLL devices. The embedded PLLs
meet and exceed the features offered by these high-end discrete devices,
reducing the need for other timing devices in the system.
Referenced
Documents
This chapter references the following documents:
■
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
■
the Stratix II GX Device Handbook (or the Stratix II Device Handbook)
■
Device Handbook (or the Stratix II Device Handbook)
■
volume 2 of the Stratix II GX Device Handbook (or the Stratix II Device
Handbook)
■
Handbook