Altera Corporation
5鈥�39
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
tM4KDATAASU
A port data setup time
before clock
22
23
25
29
ps
tM4KDATAAH
A port data hold time
after clock
203
213
233
272
ps
tM4KADDRASU
A port address setup
time before clock
22
23
25
29
ps
tM4KADDRAH
A port address hold time
after clock
203
213
233
272
ps
tM4KDATABSU
B port data setup time
before clock
22
23
25
29
ps
tM4KDATABH
B port data hold time
after clock
203
213
233
272
ps
tM4KRADDRBSU B port address setup
time before clock
22
23
25
29
ps
tM4KRADDRBH
B port address hold time
after clock
203
213
233
272
ps
tM4KDATACO1
Clock-to-output delay
when using output
registers
334
524
334
549
319
334
601
334
701
ps
tM4KDATACO2
Clock-to-output delay
without output registers
1,616
2,453
1,616
2,574
1,540
1,616
2,820
1,616
3,286
ps
tM4KCLKH
Minimum clock high time 1,250
1,312
1,437
1,675
ps
tM4KCLKL
Minimum clock low time
1,250
1,312
1,437
1,675
ps
tM4KCLR
Minimum clear pulse
width
144
151
165
192
ps
(1)
FMAX of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
(2)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3)
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4)
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5)
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
(6)
Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes
that use locally routed or non-identical sources for the A and B port registers.
Table 5鈥�41. M4K Block Internal Timing Microparameters (Part 2 of 2)
Note (1)
Symbol
Parameter
-3 Speed
Grade (2)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Unit
Min
(4)
Max
Min
(4)
Max
Min
(5)
Max
Min
(4)
Max
