鍨嬭櫉锛� | EP2S60F484C5N |
寤犲晢锛� | Altera |
鏂囦欢闋佹暩(sh霉)锛� | 491/768闋� |
鏂囦欢澶у皬锛� | 0K |
鎻忚堪锛� | IC STRATIX II FPGA 60K 484-FBGA |
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Three Reasons to Use FPGA's in Industrial Designs |
妯欐簴鍖呰锛� | 20 |
绯诲垪锛� | Stratix® II |
LAB/CLB鏁�(sh霉)锛� | 3022 |
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 60440 |
RAM 浣嶇附瑷堬細 | 2544192 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 334 |
闆绘簮闆诲锛� | 1.15 V ~ 1.25 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | 0°C ~ 85°C |
灏佽/澶栨锛� | 484-BBGA |
渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 484-FBGA锛�23x23锛� |
閰嶇敤锛� | 544-1700-ND - DSP KIT W/STRATIX II EP2S60N 544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N |
鍏跺畠鍚嶇ū锛� | 544-1908 EP2S60F484C5N-ND |
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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ASC49DRTS-S734 | CONN EDGECARD 98POS DIP .100 SLD |
EP1S25F672I7N | IC STRATIX FPGA 25K LE 672-FBGA |
ASC49DRES-S734 | CONN EDGECARD 98POS .100 EYELET |
EP1S20F780I6N | IC STRATIX FPGA 20K LE 780-FBGA |
BR24L08F-WE2 | IC EEPROM 8KBIT 400KHZ 8SOP |
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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EP2S60F484I4 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S60F484I4N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S60F672C3 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S60F672C3N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
EP2S60F672C4 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 492 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |