5–8
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Operating Conditions
Table 5–10. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
2.375
2.500
2.625
V
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100
Ω
250
450
mV
VOCM
Output common mode
voltage
RL = 100
Ω
1.125
1.375
V
RL
Receiver differential input
discrete resistor (external to
Stratix II devices)
90
100
110
Ω
Table 5–11. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
I/O supply voltage for top
and bottom PLL banks (9,
10, 11, and 12)
3.135
3.300
3.465
V
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100
Ω
250
710
mV
VOCM
Output common mode
voltage
RL = 100
Ω
840
1,570
mV
RL
Receiver differential input
discrete resistor (external to
Stratix II devices)
90
100
110
Ω
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.