
Altera Corporation
5–83
April 2011
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Row DDIO Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Port (No PLL in the Clock Path)
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS/
HyperTransport
Technology
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
3.3 V
3.3-V LVTTL
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS/ HyperTransport
technology
180
ps
(1)
(2)
The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
1.2-V
HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
3.3-V LVTTL
260
380
145
ps
3.3-V LVCMOS
210
330
100
ps
2.5 V
195
315
85
ps