
7–34
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Active Serial Configuration (Serial Configuration Devices)
Figure 7–11 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
Figure 7–11. Stratix II and Stratix II GX FPP Configuration Using an Enhanced Configuration Device Timing
Waveform
(1)
The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
f
Handbook.
f
Device configuration options and how to create configuration files are
Configuration Handbook.
Active Serial
Configuration
(Serial
Configuration
Devices)
In the AS configuration scheme, Stratix II and Stratix II GX devices are
configured using a serial configuration device. These configuration
devices are low-cost devices with non-volatile memory that feature a
simple four-pin interface and a small form factor. These features make
serial configuration devices an ideal low-cost configuration solution.
Note that AS mode is only applicable for 3.3-V configurations. If I/O
bank 3 is less than 3.3 V, level shifters are required on the output pins
(DCLK, nCSO, ASDO) from the Stratix II or Stratix II GX device back to the
EPCS device.
1
If VCCIO in bank 3 is set to 1.8 V, an external voltage level
translator is needed to meet the VIH of the EPCS device (3.3 V).
Tri-State
User Mode
tLOE
tLC
tHC
tCE
tOE
byte
2
n
byte
1
Driven High
Tri-State
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA[7..0]
User I/O
INIT_DONE
nINIT_CONF or
VCC/nCONFIG
tCD2UM (1)