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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP2S60F484C3N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 48/768闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX II FPGA 60K 484-FBGA
鐢㈠搧鍩硅〒妯″锛� Three Reasons to Use FPGA's in Industrial Designs
妯欐簴鍖呰锛� 20
绯诲垪锛� Stratix® II
LAB/CLB鏁�(sh霉)锛� 3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 60440
RAM 浣嶇附瑷堬細 2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛� 334
闆绘簮闆诲锛� 1.15 V ~ 1.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 484-FBGA锛�23x23锛�
閰嶇敤锛� 544-1700-ND - DSP KIT W/STRATIX II EP2S60N
544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛� 544-1906
EP2S60F484C3N-ND
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Altera Corporation
4鈥�1
May 2007
4. Hot Socketing &
Power-On Reset
Stratix II devices offer hot socketing, which is also known as hot plug-in
or hot swap, and power sequencing support without the use of any
external devices. You can insert or remove a Stratix II board in a system
during system operation without causing undesirable effects to the
running system bus or the board that was inserted into the system.
The hot socketing feature also removes some of the difficulty when you
use Stratix II devices on printed circuit boards (PCBs) that also contain a
mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the Stratix II hot
socketing feature, you no longer need to ensure a proper power-up
sequence for each device on the board.
The Stratix II hot socketing feature provides:
鈻�
Board or device insertion and removal without external components
or board manipulation
鈻�
Support for any power-up sequence
鈻�
Non-intrusive I/O buffers to system buses during hot insertion
This chapter also discusses the power-on reset (POR) circuitry in Stratix II
devices. The POR circuitry keeps the devices in the reset state until the
VCC is within operating range.
Stratix II
Hot-Socketing
Specifications
Stratix II devices offer hot socketing capability with all three features
listed above without any external components or special design
requirements. The hot socketing feature in Stratix II devices allows:
鈻�
The device can be driven before power-up without any damage to
the device itself.
鈻�
I/O pins remain tri-stated during power-up. The device does not
drive out before or during power-up, thereby affecting other buses in
operation.
鈻�
Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies.
External input signals to I/O pins of the device do not internally
power the VCCIO or VCCINT power supplies of the device via internal
paths within the device.
SII51004-3.2
鐩搁棞PDF璩囨枡
PDF鎻忚堪
93LC56BT/SN IC EEPROM 2KBIT 3MHZ 8SOIC
93LC56BT-I/SN IC EEPROM 2KBIT 3MHZ 8SOIC
EP2S60F484I4N IC STRATIX II FPGA 60K 484-FBGA
24LC04BT-I/SN IC EEPROM 4KBIT 400KHZ 8SOIC
APA1000-BG456 IC FPGA PROASIC+ 1M 456-PBGA
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EP2S60F484C5 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F484C5N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F484I4 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏у祵寮忓RAM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256