鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EP1S60F1508C7N
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 599/864闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX FPGA 60K LE 1508-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 7
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 5712
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 57120
RAM 浣嶇附瑷�(j矛)锛� 5215104
杓稿叆/杓稿嚭鏁�(sh霉)锛� 1022
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1508-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1508-FBGA锛�30x30锛�
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7鈥�60
Altera Corporation
Stratix Device Handbook, Volume 2
September 2004
Arithmetic Functions
Magnitude
Phase angle
= tan-1(b/a)
This conversion is useful in different applications, such as position
control and position monitoring in robotics. It is also important to have
these transformations at very high speeds to accommodate real-time
processing.
Arithmetic Function Implementation
A common approach to implementing these arithmetic functions is using
the coordinate rotation digital computer (CORDIC) algorithm. The
CORDIC algorithm calculates the trigonometric functions of sine, cosine,
magnitude, and phase using an iterative process. It is made up of a series
of micro-rotations of the vector by a set of predetermined constants,
which are powers of 2.
Using binary arithmetic, this algorithm essentially replaces multipliers
with shift and add operations. In Stratix devices, it is possible to calculate
some of these arithmetic functions directly, without having to implement
the CORDIC algorithm.
This section describes a design example that calculates the magnitude of
a 9-bit signed vector (a,b) using a pipelined version of the square root
function available at the Altera IP Megastore. To calculate the sum of the
squares of the input (a2 + b2), configure the DSP block in the two-
multipliers adder mode. The square root function is implemented using
an iterative algorithm similar to the long division operation. The binary
numbers are paired off, and subtracted by a trial number. Depending on
if the remainder is positive or negative, each bit of the square root is
determined and the process is repeated. This square root function does
not require memory and is implemented in logic cells only.
In this example, the input bit precision (IN_PREC) feeding into the square
root macro is set to twenty, and the output precision (OUT_PREC) is set to
ten. The number of precision bits is parameterizable. Also, there is a third
parameter, PIPELINE, which controls the architecture of the square root
macro. If this parameter is set to YES, it includes pipeline stages in the
square root macro. If set to NO, the square root macro becomes a single-
cycled combinatorial function.
Figure 7鈥�38 shows the implementation the magnitude design.
ma
2
b
2
+
=
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
APA300-CQ352B IC FPGA PROASIC+ 300K 352-CQFP
A42MX36-CQ256 IC FPGA MX SGL CHIP 54K 256-CQFP
93C46AT-I/ST IC EEPROM 1KBIT 2MHZ 8TSSOP
EP2AGX260FF35C6 IC ARRIA II GX 260K 1152FBGA
EP2AGX190FF35I5N IC ARRIA II GX 190K 1152FBGA
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