
4–76
Altera Corporation
Stratix Device Handbook, Volume 1
January 2006
Timing Model
Maximum Input & Output Clock Rates
column and row pins in Stratix devices.
Table 4–114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12]
Pins in Flip-Chip Packages (Part 1 of 2)
I/O Standard
-5 Speed
Grade
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
Unit
LVTTL
422
390
MHz
2.5 V
422
390
MHz
1.8 V
422
390
MHz
1.5 V
422
390
MHz
LVCMOS
422
390
MHz
GTL
300
250
200
MHz
GTL+
300
250
200
MHz
SSTL-3 Class I
400
350
300
MHz
SSTL-3 Class II
400
350
300
MHz
SSTL-2 Class I
400
350
300
MHz
SSTL-2 Class II
400
350
300
MHz
SSTL-18 Class I
400
350
300
MHz
SSTL-18 Class II
400
350
300
MHz
1.5-V HSTL Class I
400
350
300
MHz
1.5-V HSTL Class II
400
350
300
MHz
1.8-V HSTL Class I
400
350
300
MHz
1.8-V HSTL Class II
400
350
300
MHz
3.3-V PCI
422
390
MHz
3.3-V PCI-X 1.0
422
390
MHz
Compact PCI
422
390
MHz
AGP 1
×
422
390
MHz
AGP 2
×
422
390
MHz
CTT
300
250
200
MHz
Differential 1.5-V HSTL
C1
400
350
300
MHz
645
622
MHz
300
275
MHz