Stratix, Stratix II, Cyclone<" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S60F1020C7
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 78/864闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC STRATIX FPGA 60K LE 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 8
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 5712
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 57120
RAM 浣嶇附瑷堬細 5215104
杓稿叆/杓稿嚭鏁�(sh霉)锛� 773
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1434
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Altera Corporation
3鈥�5
July 2005
Stratix Device Handbook, Volume 1
Configuration & Testing
1
Stratix, Stratix II, Cyclone, and Cyclone II devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they will
fail configuration. This does not affect SignalTap II.
f
For more information on JTAG, see the following documents:
鈻�
AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
鈻�
Jam Programming & Test Language Specification
SignalTap II
Embedded Logic
Analyzer
Stratix devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE Std.
1149.1 (JTAG) circuitry. You can analyze internal logic at speed without
bringing internal signals to the I/O pins. This feature is particularly
important for advanced packages, such as FineLine BGA packages,
because it can be difficult to add a connection to a pin during the
debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix architecture are
configured with CMOS SRAM elements. Altera devices are
reconfigurable. Because every device is tested with a high-coverage
production test program, you do not have to perform fault testing and can
focus on simulation and design verification.
Stratix devices are configured at system power-up with data stored in an
Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix devices via a serial data stream. Stratix
devices can be configured in under 100 ms using 8-bit parallel data at
100 MHz. The Stratix device鈥檚 optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
or asynchronously. The interface also enables microprocessors to treat
Stratix devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix device has
been configured, it can be reconfigured in-circuit by resetting the device
and loading new data. Real-time changes can be made during system
operation, enabling innovative reconfigurable computing applications.
Operating Modes
The Stratix architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
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PDF鎻忚堪
A42MX36-1CQ208 IC FPGA MX SGL CHIP 54K 208-CQFP
A54SX16-1CQ208M IC FPGA SX 24K GATES 208-CQFP
A14100A-CQ256C IC FPGA 10K GATES 256-CQFP
A54SX32-CQ208 IC FPGA SX 48K GATES 208-CQFP
EP1S60F1508C7N IC STRATIX FPGA 60K LE 1508-FBGA
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鍙冩暩(sh霉)鎻忚堪
EP1S60F1020C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1508C5ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix Device Family Data Sheet
EP1S60F1508C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 1022 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256