Altera
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S60F1020C7
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 755/864闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX FPGA 60K LE 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯欐簴鍖呰锛� 8
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 5712
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 57120
RAM 浣嶇附瑷堬細 5215104
杓稿叆/杓稿嚭鏁�(sh霉)锛� 773
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1434
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Altera Corporation
12鈥�1
September 2004
12. Remote System
Configuration with Stratix &
Stratix GX Devices
Introduction
Altera Stratix and Stratix GX devices are the first programmable logic
devices (PLDs) featuring dedicated support for remote system
configuration. Using remote system configuration, a Stratix or Stratix GX
device can receive new configuration data from a remote source, update
the flash memory content (through enhanced configuration devices or
any other storage device), and then reconfigure itself with the new data.
Like all Altera SRAM-based devices, Stratix and Stratix GX devices
support standard configuration modes such as passive serial (PS), fast
passive parallel (FPP), and passive parallel asynchronous (PPA). You can
use the standard configuration modes with remote system configuration.
This chapter discusses remote system configuration of Stratix and Stratix
GX devices, and how to interface them with enhanced configuration
devices to enable this capability. This document also explains some
related remote system configuration topics, such as the watchdog timer,
remote system configuration registers, and factory or application
configurations files. The Quartus II software (version 2.1 and later)
supports remote system configuration.
Remote
Configuration
Operation
Remote system configuration has three major parts:
鈻�
The Stratix or Stratix GX device receives updated or new data from a
remote source over a network (or through any other source that can
transfer data). You can implement a Nios (16-bit ISA) or Nios II
(32-bit ISA) embedded processor within either a Stratix or Stratix GX
device or an external processor to control the read and write
functions of configuration files from the remote source to the
memory device.
鈻�
The new or updated information is stored into the memory device,
which can be an enhanced configuration device, industry-standard
flash memory device, or any other storage device (see Figure 12鈥�2).
鈻�
The Stratix or Stratix GX device updates itself with the new data from
the memory.
Figure 12鈥�1 shows the concept of remote system configuration in Stratix
and Stratix GX devices.
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PDF鎻忚堪
A42MX36-1CQ208 IC FPGA MX SGL CHIP 54K 208-CQFP
A54SX16-1CQ208M IC FPGA SX 24K GATES 208-CQFP
A14100A-CQ256C IC FPGA 10K GATES 256-CQFP
A54SX32-CQ208 IC FPGA SX 48K GATES 208-CQFP
EP1S60F1508C7N IC STRATIX FPGA 60K LE 1508-FBGA
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EP1S60F1020C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1508C5ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix Device Family Data Sheet
EP1S60F1508C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 1022 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256