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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� EP1S60F1020C7
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 200/864闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC STRATIX FPGA 60K LE 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Three Reasons to Use FPGA's in Industrial Designs
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� Package Height Change 03/March/2008
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 8
绯诲垪锛� Stratix®
LAB/CLB鏁�(sh霉)锛� 5712
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 57120
RAM 浣嶇附瑷堬細 5215104
杓稿叆/杓稿嚭鏁�(sh霉)锛� 773
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 1020-FBGA锛�33x33锛�
鍏跺畠鍚嶇ū锛� 544-1434
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Altera Corporation
4鈥�99
January 2006
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
卤50
ps
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
卤75
ps
fSS
Spread spectrum modulation
frequency
30
150
kHz
% spread
Percentage spread for spread
spectrum frequency (10)
0.5
0.6
%
tARESET
Minimum pulse width on areset
signal
10
ns
(1)
The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs.
(2)
Use this equation (fOUT = fIN * ml(n 脳 post-scale counter)) in conjunction with the specified fINPFD and fVCO ranges
to determine the allowed PLL settings.
(3)
(4)
tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(5)
This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
(6)
Actual jitter performance may vary based on the system configuration.
(7)
Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are
changed, then tDLOCK is equal to 0.
(8)
When using the spread-spectrum feature, the minimum VCO frequency is 500 MHz. The maximum VCO
frequency is determined by the speed grade selected.
(9)
Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
(10) Exact, user-controllable value depends on the PLL settings.
(11) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
Table 4鈥�130. Enhanced PLL Specifications for -8 Speed Grade (Part 3 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
EP1S60F1020C7N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1020I6N 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 773 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP1S60F1508C5ES 鍒堕€犲晢:ALTERA 鍒堕€犲晢鍏ㄧū:Altera Corporation 鍔熻兘鎻忚堪:Stratix Device Family Data Sheet
EP1S60F1508C6 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix I 5712 LABs 1022 IO RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256