- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97914 > EP1K50TI144-2X Field Programmable Gate Array (FPGA) PDF資料下載
參數(shù)資料
| 型號： | EP1K50TI144-2X |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 7/86頁 |
| 文件大小： | 1263K |
| 代理商： | EP1K50TI144-2X |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
Altera Corporation
15
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as
clocks, the other two can be used for clear/preset control. The LAB clocks
can be driven by the dedicated clock input pins, global signals, I/O
signals, or internal signals via the LAB local interconnect. The LAB preset
and clear control signals can be driven by the global signals, I/O signals,
or internal signals via the LAB local interconnect. The global control
signals are typically used for global clock, clear, or preset signals because
they provide asynchronous control with very low skew across the device.
If logic is required on a control signal, it can be generated in one or more
LEs in any LAB and driven into the local interconnect of the target LAB.
In addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure. Figure 8 shows the ACEX 1K LE.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP1K50TI144-3F | Field Programmable Gate Array (FPGA) |
| EP20K100RC208-1 | High Power LED Driver; Temperature Range: -25°C to 85°C; Package: 20-QFN |
| EP20K100RC208-1ES | High Power LED Driver; Temperature Range: -25°C to 85°C; Package: 20-QFN T&R |
| EP20K100RC208-2 | Advanced 170MHz Triple Video Digitizer with Digital PLL; Temperature Range: 0°C to 70°C; Package: 128-MQFP |
| EP20K100RC208-2ES | Advanced 240MHz Triple Video Digitizer with Digital PLL; Temperature Range: 0°C to 70°C; Package: 128-MQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50TI144-3F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1M120 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EP1M120F484C5 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 480 LABs 303 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1M120F484C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 480 LABs 303 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1M120F484C6 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - MERCURY 480 LABs 303 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。