參數(shù)資料
型號(hào)： EP1K50FI484-1X
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA）
文件頁(yè)數(shù)： 18/86頁(yè)
文件大?。?/td> 1263K
代理商： EP1K50FI484-1X
Altera Corporation
25
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode,
the preset signal is tied to VCC to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
register’s input and output. Inversion control is available for the inputs to
both LEs and IOEs. Therefore, if a register is preset by only one of the two
LABCTRL
signals, the DATA3 input is not needed and can be used for one of
the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset, and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling the
register preset and clear. LABCTRL2 implements the clear by controlling
the register clear; LABCTRL2 does not have to feed the preset circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling the
register preset and clear.
相關(guān)PDF資料
PDF描述
EP1K50FI484-2DX Field Programmable Gate Array (FPGA)
EP1K50FI484-2F Field Programmable Gate Array (FPGA)
EP1K50FI484-2P Field Programmable Gate Array (FPGA)
EP1K50FI484-2X Field Programmable Gate Array (FPGA)
EP1K50FI484-3F Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP1K50FI484-2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述:
EP1K50FI484-2DX 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2F 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2P 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2X 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
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