參數(shù)資料
型號(hào)： EN29LV040A
廠商： Electronic Theatre Controls, Inc.
英文描述： 4 Megabit (512K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory
中文描述： 4兆位（為512k × 8位）統(tǒng)一部門，3.0伏的CMOS只閃存
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 257K
代理商： EN29LV040A
This Data Sheet may be revised by subsequent versions 2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2005/08/16
EN29LV040A
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low V
CC
Write Inhibit
When Vcc is less than V
LKO
, the device does not accept any write cycles. This protects data during
Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V
LKO
. The
system must provide the proper signals to the control pins to prevent unintentional writes when Vcc
is greater than V
LKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on
OE
,
CE
or
W E
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE
= VIL,
CE
= VIH, or
W E
= VIH. To initiate a
write cycle,
CE
and
W E
must be a logical zero while
OE
is a logical one. If
CE
,
W E
, and
OE
are
all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with
CE
= V
IL
,
WE
= V
IL
and
OE
= V
IH
, the device will not accept commands on the rising edge of
W E
.
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