參數(shù)資料
型號： EFM32TG840F32
廠商： Energy Micro
文件頁數(shù)： 45/136頁
文件大小： 0K
描述： MCU 32BIT 32KB FLASH 64-QFN
特色產品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設備： 欠壓檢測/復位，DMA，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉換器： A/D 8x12b，D/A 2x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 標準包裝
其它名稱： 914-1036-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
16
www.energymicro.com
Device
The processor preserves transaction order relative to other transactions to
Device or Strongly-ordered memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory
system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
The additional memory attributes include.
Execute Never (XN)
Means the processor prevents instruction accesses. Any attempt to fetch an
instruction from an XN region causes a memory management fault exception.
2.2.2 Memory system ordering of memory accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions,
providing this does not affect the behavior of the instruction sequence. Normally, if correct program
execution depends on two memory accesses completing in program order, software must insert a
memory barrier instruction between the memory access instructions, see Section 2.2.4 (p. 17) .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-
ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program
order, the ordering of the memory accesses caused by two instructions is:
Norm al access
Device access, non-shareable
Device access, shareable
St rongly-ordered access
Norm al
access
Non-shareable
Shareable
St rongly-
ordered
access
Device access
A1
A2
-
<
-
<
-
<
-
<
Where:
-
Means that the memory system does not guarantee the ordering of the accesses.
<
Means that accesses are observed in program order, that is, A1 is always observed before A2.
2.2.3 Behavior of memory accesses
The behavior of accesses to each region in the memory map is:
Table 2.11. Memory access behavior
Address
range
Memory region
Memory
type
XN
Description
0x00000000
-
0x1FFFFFFF
Code
Normal
1
-
Executable region for program code. You can also put data here.
0x20000000
-
0x3FFFFFFF
SRAM
Normal
1
-
Executable region for data. You can also put code here.This region
includes bit band and bit band alias areas, see Table 2.12 (p. 18)
.
0x40000000
-
0x5FFFFFFF
Peripheral
Device
1
XN
1
This region includes bit band and bit band alias areas, see
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