參數(shù)資料
型號(hào): EFM32TG840F32
廠商: Energy Micro
文件頁(yè)數(shù): 21/136頁(yè)
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 64-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤(pán)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): 914-1036-6
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...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
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4.5.4 MPU Region Base Address Register
The RBAR defines the base address of the MPU region selected by the RNR, and can update the value
of the RNR. See the register summary in Table 4.38 (p. 114) for its attributes.
Write RBAR with the VALID bit set to 1 to change the current region number and update the RNR. The
bit assignments are:
VALID
ADDR
31
N N-1
5 4 3
0
Reserved
REGION
If t he region size is 32B, t he ADDR field is bit s [ 31:5] and t here is no Reserved field
Table 4.42. RBAR bit assignments
Bits
Name
Function
[31:N]
ADDR
Region base address field. The value of N depends on the region size. For more information see
[(N-1):5]
-
Reserved.
[4]
VALID
MPU Region Number valid bit:
Write:
0 = RNR not changed, and the processor:
updates the base address for the region specified in the RNR
ignores the value of the REGION field
1 = the processor:
updates the value of the RNR to the value of the REGION field
updates the base address for the region specified in the REGION field.
Always reads as zero.
[3:0]
REGION
MPU region field:
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the RNR.
4.5.4.1 The ADDR field
The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field in the RASR,
defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this case, the region
occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must be aligned on
a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
4.5.5 MPU Region Attribute and Size Register
The RASR defines the region size and memory attributes of the MPU region specified by the RNR,
and enables that region and any subregions. See the register summary in Table 4.38 (p. 114) for
its attributes.
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