參數(shù)資料
型號: EFM32TG232F32
廠商: Energy Micro
文件頁數(shù): 133/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32KB FLASH 64LQFP
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1030-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
96
www.energymicro.com
Bits
Name
Function
[2]
DISFOLD
When set to 1, disables IT folding. see Section 4.3.2.1 (p. 96) for more information.
[1]
DISDEFWBUF
When set to 1, disables write buffer use during default memory map accesses. This causes
all bus faults to be precise bus faults but decreases performance because any store to
memory must complete before the processor can execute the next instruction.
Note
This bit only affects write buffers implemented in the Cortex-M3 processor.
[0]
DISMCYCINT
When set to 1, disables interruption of load multiple and store multiple instructions. This
increases the interrupt latency of the processor because any LDM or STM must complete
before the processor can stack the current state and enter the interrupt handler.
4.3.2.1 About IT folding
In some situations, the processor can start executing the first instruction in an IT block while it is still
executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT
folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing
the task, to disable IT folding.
4.3.3 CPUID Base Register
The CPUID register contains the processor part number, version, and implementation information. See
the register summary in Table 4.12 (p. 94) for its attributes. The bit assignments are:
31
16 15
4 3
0
Im plem ent er
Revision
Part No
24 23
20 19
Variant
Const ant
Table 4.14. CPUID register bit assignments
Bits
Name
Function
[31:24]
Implementer
Implementer code:
0x41
= ARM
[23:20]
Variant
Variant number, the r value in the rnpn product revision identifier:
0x2
= r2pX
[19:16]
Constant
Reads as 0xF
[15:4]
PartNo
Part number of the processor:
0xC23
= Cortex-M3
[3:0]
Revision
Revision number, the p value in the rnpn product revision identifier:
0x0
= rXp0
0x1
= rXp1
4.3.4 Interrupt Control and State Register
The ICSR:
provides:
a set-pending bit for the Non-Maskable Interrupt (NMI) exception
set-pending and clear-pending bits for the PendSV and SysTick exceptions
indicates:
the exception number of the exception being processed
whether there are preempted active exceptions
the exception number of the highest priority pending exception
whether any interrupts are pending.
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