參數(shù)資料
型號： EFM32TG222F32
廠商： Energy Micro
文件頁數(shù)： 92/136頁
文件大小： 0K
描述： IC MCU 32BIT 32KB FLASH 48LQFP
特色產品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設備： 欠壓檢測/復位，DMA，I²S，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據轉換器： A/D 4x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-TQFP
包裝： 標準包裝
其它名稱： 914-1029-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
59
www.energymicro.com
3.5.1.6 Multiword arithmetic examples
Example 3.4 (p. 59) shows two instructions that add a 64#bit integer contained in R2 and R3 to
another 64#bit integer contained in R0 and R1, and place the result in R4 and R5.
Example 3.4. 64-bit addition
ADDS
R4, R0, R2
; add the least significant words
ADC
R5, R1, R3
; add the most significant words with carry
Multiword values do not have to use consecutive registers. Example 3.5 (p. 59) shows instructions
that subtract a 96#bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8.
The example stores the result in R6, R9, and R2.
Example 3.5. 96-bit subtraction
SUBS
R6, R6, R9
; subtract the least significant words
SBCS
R9, R2, R1
; subtract the middle words with carry
SBC
R2, R8, R11
; subtract the most significant words with carry
3.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
3.5.2.1 Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op
is one of:
AND
logical AND.
ORR
logical OR, or bit set.
EOR
logical Exclusive OR.
BIC
logical AND NOT, or bit clear.
ORN
logical OR NOT.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result of
the operation, see Section 3.3.7 (p. 43) .
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
is the destination register.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
3.5.2.2 Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the
values in Rn and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the
corresponding bits in the value of Operand2.
3.5.2.3 Restrictions
Do not use SP and do not use PC.
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