
EDS2732CABH
Data Sheet E0397E40 (Ver. 4.0)
8
Test Conditions
Input and output timing reference levels: 1.2V
Input waveform and output load: See following figures
tT
2.1V
1.7V
0.7V
0.3V
input
t
T
I/O
CL
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-75
-1A
Frequency (MHz)
133
100
tCK (ns)
Symbol
7.5
10
Unit
Notes
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
l
RCD
3
2
tCK
1
l
RC
9
7
tCK
1
l
RAS
6
5
tCK
1
l
RP
3
2
tCK
1
l
DPL
2
2
tCK
1
l
RRD
2
2
tCK
1
Self refresh exit time
l
SREX
1
1
tCK
2
Last data in to active command
(Auto precharge, same bank)
l
DAL
5
4
tCK
= [
l
DPL +
l
RP]
Self refresh exit to command input
l
SEC
9
7
tCK
= [
l
RC]
3
Precharge command to high impedance
(CL = 2)
l
HZP
—
2
tCK
(CL = 3)
l
HZP
3
3
tCK
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early
precharge)
(CL = 2)
l
APR
1
1
tCK
l
EP
—
–1
tCK
(CL = 3)
l
EP
–2
–2
tCK
Column command to column command
l
CCD
1
1
tCK
Write command to data in latency
l
WCD
0
0
tCK
DQM to data in
l
DID
0
0
tCK
DQM to data out
l
DOD
2
2
tCK
CKE to CLK disable
l
CLE
1
1
tCK
Register set to active command
l
MRD
2
2
tCK
/CS to command disable
l
CDD
0
0
tCK
Power down exit to command input
l
PEC
1
1
tCK
Notes: 1.
l
RCD to
l
RRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]