參數(shù)資料
型號(hào)： EDS2516APTA-TI-E
廠商： Elpida Memory, Inc.
英文描述： 256M bits SDRAM WTR (Wide Temperature Range)
中文描述： 256M比特內(nèi)存水樹(shù)（寬溫度范圍）
文件頁(yè)數(shù)： 40/50頁(yè)
文件大?。?/td> 703K
代理商： EDS2516APTA-TI-E
EDS2516CDTA
Refresh
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
40
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-
refresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a
self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or
within tREF (max.) period on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after
exiting from self-refresh mode.
Note: tREF (max.) / refresh cycles.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
相關(guān)PDF資料
PDF描述
EDS2516ACTA 256M bits SDRAM
EDS2516ACTA-75 256M bits SDRAM
EDS2516ACTA-7A 256M bits SDRAM
EDS2516ADTA-75 256M bits SDRAM (16M words x 16 bits)
EDS2516ADTA-75-E 256M bits SDRAM (16M words x 16 bits)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDS2516CDTA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM (16M words x 16 bits)
EDS2516CDTA-75-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM (16M words x 16 bits)
EDS2516EEBH-9ATT-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM WTR (Wide Temperature Range)
EDS2516EEBH-TT 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM WTR (Wide Temperature Range)
EDS2516JEBH-75R3 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits AS SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*