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參數資料
| 型號： | EDI9LC644V-BC |
| 英文描述： | Programmable VCOM; Temperature Range: -40°C to 85°C; Package: 12-DFN T&R |
| 中文描述： | 的SSRAM / SDRAM的MCP的 |
| 文件頁數： | 7/25頁 |
| 文件大?。?/td> | 1551K |
| 代理商： | EDI9LC644V-BC |
15
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI9LC644V
FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
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