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參數資料
| 型號： | EDI9LC644V-BC |
| 英文描述： | Programmable VCOM; Temperature Range: -40°C to 85°C; Package: 12-DFN T&R |
| 中文描述： | 的SSRAM / SDRAM的MCP的 |
| 文件頁數： | 16/25頁 |
| 文件大?。?/td> | 1551K |
| 代理商： | EDI9LC644V-BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
EDI9LC644V
FIG. 16
SDRAM MODE REGISTER SET CYCLE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS activation.
7. Please refer to Mode Register Set table.
SDRAM AUTO REFRESH CYCLE
HIGH
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