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參數(shù)資料
| 型號： | EDI9LC644V-BC |
| 英文描述： | Programmable VCOM; Temperature Range: -40°C to 85°C; Package: 12-DFN T&R |
| 中文描述： | 的SSRAM / SDRAM的MCP的 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 1551K |
| 代理商： | EDI9LC644V-BC |
14
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
EDI9LC644V
FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2 Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will
be Hi-Z (tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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