參數(shù)資料
型號： EDE5116AJBG-6E-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR2 SDRAM
中文描述： 32M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝： ROHS COMPLIANT, FBGA-84
文件頁數(shù)： 53/77頁
文件大?。?/td> 589K
代理商： EDE5116AJBG-6E-E
EDE5108AJBG, EDE5116AJBG
Preliminary Data Sheet E1044E20 (Ver. 2.0)
53
Burst Write Command [WRIT]
The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of
the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read
latency (RL) minus one and is equal to (AL + CL
1). A data strobe signal (DQS) should be driven low (preamble)
one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge
of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent
burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst
has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst
write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery
time (tWR).
WRIT
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T9
Command
DQS, /DQS
DQ
in2
PRE
NOP
ACT
in1
in3
in0
WL = RL –1 = 2
≤
tDQSS
≥
tRP
≥
tWR
Completion of
the burst write
Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))
WRIT
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
≥
tRP
≥
tWR
in2
in1
in3
in0
in6
in5
in7
in4
WL = RL –1 = 2
T9
T11
NOP
ACT
PRE
≤
tDQSS
Completion of
the burst write
Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))
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