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參數(shù)資料
| 型號： | EDE5108GBSA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits DDR-II SDRAM |
| 中文描述： | 512M比特的DDR - II內(nèi)存 |
| 文件頁數(shù)： | 17/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5108GBSA |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
17
DM, UDM and LDM
(input pins)
DM is an input mask signal for write data. In 32M
×
16 products, UDM and LDM control upper byte (DQ8 to DQ15)
and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled high coincident with that input data during
a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading. For
×
8 configuration, DM function will be disabled when RDQS function is enabled by
EMRS.
DQ (input/output pins)
Bi-directional data bus.
DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins)
Output with read data, input with write data for source synchronous operation. In 32M
×
16 products, UDQS, /UDQS
and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data,
centered in write data. Used to capture write data. /DQS can be disabled by EMRS.
RDQS, /RDQS (output pins)
Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins
exist only in
×
8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS
.
ODT (input pins)
ODT (On Die Termination control) is a registered high signal that enables termination resistance internal to the DDR
II SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for
×
4,
×
8
configurations. For
×
16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM
signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.
VDD, VSS, VDDQ, VSSQ (power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
VDDL and VSSDL (power supply)
VDDL and VSSDL are power supply pins for DLL circuits.
VREF (Power supply)
SSTL_18 reference voltage: (0.50
±
0.01)
×
VDDQ
相關PDF資料 |
PDF描述 |
|---|---|
| EDE5104AESK | 512M bits DDR2 SDRAM |
| EDE5104AESK-4A-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5108GBSA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5108GBSA-5A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM |
| EDE5116ABSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116ABSE-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5116ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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