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參數(shù)資料
| 型號： | EDE5108AESK |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 512M比特DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 7/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5108AESK |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
7
DC Characteristics 1 (TC = 0 to +85
°
C, VDD, VDDQ = 1.8V
±
0.1V)
max.
×
4
Parameter
Symbol
Grade
×
8
×
16
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-PRE)
IDD0
-5C
-4A
105
90
110
95
155
140
mA
Operating current
(ACT-READ-PRE)
IDD1
-5C
-4A
120
105
125
110
170
155
mA
Precharge power-
-5C
-4A
10
8
10
8
10
8
mA
Precharge quiet
standby current
IDD2Q
-5C
-4A
25
20
25
20
25
20
mA
Idle standby current
IDD2N
-5C
-4A
30
25
30
25
30
25
mA
IDD3P-F -4A
40
35
40
35
40
35
mA
Fast PDN Exit
MRS(12) = 0
Active power-down
standby current
IDD3P-S
-5C
-4A
25
20
25
20
25
20
mA
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and address bus
inputs are STABLE;
Data bus inputs are FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby
current
IDD3N
-5C
-4A
65
60
65
60
85
75
mA
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
-5C
-4A
170
140
190
150
240
200
mA
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(Burst write
operating)
IDD4W
-5C
-4A
170
140
190
150
240
200
mA
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5108GBSA | 512M bits DDR-II SDRAM |
| EDE5104AESK | 512M bits DDR2 SDRAM |
| EDE5104AESK-4A-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5108AESK-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AGBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AGBG-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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