參數(shù)資料
型號： EDE5108AESK
廠商： Elpida Memory, Inc.
英文描述： 512M bits DDR2 SDRAM
中文描述： 512M比特DDR2 SDRAM內(nèi)存
文件頁數(shù)： 47/66頁
文件大?。?/td> 697K
代理商： EDE5108AESK
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
47
Precharge Command [PRE]
The precharge command is used to precharge or close a bank that has been activated. The precharge command is
triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge
command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,
BA0 and BA1 are used to define which bank to precharge when the command is issued.
[Bank Selection for Precharge by Address Bits]
A10
BA0
BA1
Precharged Bank(s)
L
L
L
Bank 0 only
L
H
L
Bank 1 only
L
L
H
Bank 2 only
L
H
H
Bank 3 only
H
×
×
All banks 0 to 3
Remark: H: VIH, L: VIL,
×
: VIH or VIL
Burst Read Operation Followed by Precharge
Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks
For the earliest possible precharge, the precharge command may be issued on the rising edge that is
“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the
same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
AL + 2 clocks
RL = 4
AL = 1
CL = 3
CL = 3
out0
out2
PRE
NOP
out1
out3
Posted
READ
ACT
NOP
>
tRP
=
=
>
tRAS
Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
RL = 5
AL = 2
>
tRAS
=
CL = 3
CL = 3
out0
out2
NOP
PRE
out1
out3
Posted
READ
ACT
NOP
>
tRP
=
AL + 2 clocks
Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))
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參數(shù)描述
EDE5108AESK-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
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