參數(shù)資料
型號: EDE5108AESK-5C-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR2 SDRAM
中文描述: 64M X 8 DDR DRAM, 0.5 ns, PBGA60
封裝: ROHS COMPLIANT, FBGA-60
文件頁數(shù): 44/66頁
文件大?。?/td> 697K
代理商: EDE5108AESK-5C-E
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
44
Posted
WRIT
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T9
Command
DQS, /DQS
DQ
WL = RL
1 = 4
>
tWR
=
in0
in1
in2
in3
PRE
=
<
tDQSS
Completion of
the Burst Write
Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
DQS, /DQS
DQ
CL = 3
RL = 5
AL = 2
>
tWTR
=
in0
in2
NOP
in1
in3
Posted
READ
WL = RL –1 = 4
Write to Read = CL - 1 + BL/2 + tWTR (2) = 6
out0
out1
Burst Write Followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3))
The minimum number of clock from the burst write command to the burst read command is CL - 1 + BL/2 + a write
to-read-turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the
4bit write data from the input buffer into sense amplifiers in the array.
NOP
/CK
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
in
A0
in
A2
NOP
in
A1
in
A3
in
B0
in
B2
in
B1
in
B3
Posted
WRIT
Posted
WRIT
WL = RL
1 = 4
A
B
Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4)
Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed
regardless of same or different banks as long as the banks are activated.
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