參數(shù)資料
型號(hào)： EDD2516AETA-7A-E
廠(chǎng)商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 256M bits DDR SDRAM
中文描述： 16M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 27/52頁(yè)
文件大?。?/td> 492K
代理商： EDD2516AETA-7A-E
EDD2508AETA, EDD2516AETA
Data Sheet E0859E50 (Ver. 5.0)
27
Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL
tCK + tAC (ns) after the clock rising
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3
out4 out5 out6 out7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
CL = 3
BL: Burst length
t1
t0
t5
t6
t7
t8
t9
t10
tRCD
tRPRE
tRPST
ACT
NOP
NOP
NOP
READ
Row
Column
t11
Read Operation (Burst Length)
相關(guān)PDF資料
PDF描述
EDD2508AETA 256M bits DDR SDRAM
EDD2508AETA-5B-E 256M bits DDR SDRAM
EDD2508AETA-5C-E 256M bits DDR SDRAM
EDD2508AETA-6B-E 256M bits DDR SDRAM
EDD2508AETA-7A-E 256M bits DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD2516AETA-7B-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:256M bits DDR SDRAM
EDD2516AKTA 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:256M bits DDR SDRAM
EDD2516AKTA-5 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:256M bits DDR SDRAM
EDD2516AKTA-5C 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:256M bits DDR SDRAM
EDD2516AKTA-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:256M bits DDR SDRAM (16M words x16 bits, DDR400)
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