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參數(shù)資料
| 型號： | EDD2508AETA-5B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits DDR SDRAM |
| 中文描述： | 32M X 8 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 1/52頁 |
| 文件大?。?/td> | 492K |
| 代理商： | EDD2508AETA-5B-E |
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Document No. E0859E50 (Ver. 5.0)
Date Published September 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007
DATA SHEET
256M bits DDR SDRAM
EDD2508AETA (32M words
×
8 bits)
EDD2516AETA (16M words
×
16 bits)
Specifications
Density: 256M bits
Organization
8M words
×
8 bits
×
4 banks (EDD2508AETA)
4M words
×
16 bits
×
4 banks (EDD2516AETA)
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply:
DDR400:
VDD, VDDQ
=
2.6V
±
0.1V
DDR333, 266: VDD, VDDQ
=
2.5V
±
0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8
μ
s
Operating ambient temperature range
TA = 0
°
C to +70
°
C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD2508AETA-5C-E | 256M bits DDR SDRAM |
| EDD2508AETA-6B-E | 256M bits DDR SDRAM |
| EDD2508AETA-7A-E | 256M bits DDR SDRAM |
| EDD2508AETA-7B-E | 256M bits DDR SDRAM |
| EDD2516AETA | 256M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD2508AETA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AJTA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
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