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參數(shù)資料
| 型號： | EDD2508AKTA-5-E |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| 中文描述： | 256M比特DDR SDRAM內(nèi)存（32M的字× 8位，支持DDR400） |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 551K |
| 代理商： | EDD2508AKTA-5-E |
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EDD2508AKTA-5-E
Preliminary Data Sheet E0609E20 (Ver. 2.0)
21
Operation of the DDR SDRAM
Power-up Sequence
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 μs.
(3) After the minimum 200 μs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
Command
EMRS
PALL
MRS
REF
2 cycles (min.)
2 cycles (min.)
200 cycles (min)
2 cycles (min.)
2 cycles (min.)
t
RP
t
RFC
t
RFC
PALL
MRS
REF
coAny
DLL enable
DLL reset with A8 = High
/CK
CK
(4)
(5)
(6)
(7)
(8)
(9)
Disable DLL reset with A8 = Low
Power-up Sequence after CKE Goes High
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command
[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are
set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine
which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode
register must be set.
Remind that no other parameters shown in the table bellow are allowed to input to the registers.
A2 A1 A0Burst Length
BT=0 BT=1
0
0
0
0
1
1
1
0
1
2
4
8
2
4
8
A3
0
1
Sequential
Interleave
Burst Type
A6 A5 A4 CAS Latency
0
1
1
3
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
DR
LMODE
BT
BL
A8
0
1
No
Yes
DLL Reset
A11
A10
A12
BA1
0
BA0
0
MRS
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
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PDF描述 |
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| EDD2508AKTA-5B-E | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5C-E | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5 | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5B | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5C | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD2508AKTA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AKTA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AKTA-6BLI | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM WTR (Wide Temperature Range) |
| EDD2508AKTA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AKTA-LI | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM WTR (Wide Temperature Range) |
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