參數(shù)資料
型號: EDD2508AETA
廠商: Elpida Memory, Inc.
英文描述: 256M bits DDR SDRAM
中文描述: 256M比特DDR內(nèi)存
文件頁數(shù): 7/52頁
文件大小: 492K
代理商: EDD2508AETA
EDD2508AETA, EDD2516AETA
Data Sheet E0859E50 (Ver. 5.0)
7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at
VIH or
VIL.
DC Characteristics 2 (TA = 0°C to +70
°
C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = 0°C to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
min.
max.
Unit
Test condition
Note
Input leakage current
ILI
–2
2
μA
VDD
VIN
VSS
Output leakage current
ILO
–5
5
μA
VDDQ
VOUT
VSS
Output high current
IOH
–15.2
mA
VOUT = 1.95V
Output low current
IOL
15.2
mA
VOUT = 0.35V
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.6V ± 0.1V, VSS, VSSQ = 0V) [DDR400]
(TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [DDR333, 266]
Parameter
Symbol
Pins
min.
typ.
max.
Unit
Notes
Input capacitance
CI1
CK, /CK
2.0
3.0
pF
1
CI2
All other input pins
2.0
3.0
pF
1
Delta input capacitance
Cdi1
CK, /CK
0.25
pF
1
Cdi2
All other input-only pins
0.5
pF
1
Data input/output capacitance
CI/O
DQ, DM, DQS
4.0
5
pF
1, 2
Delta input/output capacitance
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
VOUT = 0.2V.
2. DOUT circuits are disabled.
Cdio
DQ, DM, DQS
0.5
pF
1
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