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參數(shù)資料
| 型號： | EDD1232AABH-7A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | GT 3C 3#16S PIN PLUG |
| 中文描述： | 4M X 32 DDR DRAM, 0.75 ns, PBGA144 |
| 封裝： | ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 13/50頁 |
| 文件大?。?/td> | 621K |
| 代理商： | EDD1232AABH-7A-E |
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EDD1232AABH
Data Sheet E0533E50 (Ver. 5.0)
13
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered
when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or
write access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM0 to DM3 (input pin)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VREF.
When DM = High, the data input at the same timing are masked while the internal burst counter will be counting up.
Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
DQ0 to DQ31 (input/output pins)
Data is input to and output from these pins.
DQS0 to DQS3 (input and output pin):
DQS0 to DQS3 provide the read data strobes (as output) and the write
data strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM
Correspondence Table).
[DQS and DM Correspondence Table]
DQS
Data mask
DQs
DQS0
DM0
DQ0 to DQ7
DQS1
DM1
DQ8 to DQ15
DQS2
DM2
DQ16 to DQ23
DQS3
DM3
DQ24 to DQ31
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
MCL
(input pins)
This pin must be connected with VSS. A connection with any level other than VSS may result in undefined
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD1232ABBH | 128M bits DDR SDRAM |
| EDD1232ABBH-5C-E | 128M bits DDR SDRAM |
| EDD2504AKTA-6B-E | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA-7A-E | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2504AKTA | 256M bits DDR SDRAM (64M words x 4 bits) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1232AAFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232AAFA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (4M words x 32 bits) |
| EDD1232ABBH | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
| EDD1232ABBH-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM |
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