參數(shù)資料
型號(hào)： EDD1216AJTA-7B-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M bits DDR SDRAM
中文描述： 8M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 513K
代理商： EDD1216AJTA-7B-E
EDD1216AJTA
Data Sheet E0972E30 (Ver. 3.0)
36
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
address
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
Row address State
Operation
1. Same
Same
ACTIVE
2. Same
Different
—
3. Different
Any
ACTIVE
IDLE
in0
in1
in2
in3
out2
out0
out1
CK
/CK
DM
DQ
Command
t1
t0
t2
t3
t4
t5
t6 t7 t8
BL = 4
CL = 3
tWRD (min)
tWTR*
DQS
INPUT
OUTPUT
BL/2 + 2 cycle
WRIT
NOP
NOP
READ
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
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