參數(shù)資料
型號(hào)： EDD1216AJTA-5B-E
廠商： ELPIDA MEMORY INC
元件分類(lèi)： DRAM
英文描述： 128M bits DDR SDRAM
中文描述： 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 24/52頁(yè)
文件大?。?/td> 513K
代理商： EDD1216AJTA-5B-E
EDD1216AJTA
Data Sheet E0972E30 (Ver. 3.0)
24
Operation of the DDR SDRAM
Power-up Sequence
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 μs.
(3) After the minimum 200 μs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
Command
EMRS
PALL
MRS
REF
2 cycles (min.)
2 cycles (min.)
200 cycles (min)
2 cycles (min.)
2 cycles (min.)
t
RP
t
RFC
t
RFC
PALL
MRS
REF
coAny
DLL enable
DLL reset with A8 = High
CK
/CK
(4)
(5)
(6)
(7)
(8)
(9)
Disable DLL reset with A8 = Low
Power-up Sequence after CKE Goes High
相關(guān)PDF資料
PDF描述
EDD1216AJTA-5C-E 128M bits DDR SDRAM
EDD1216AJTA-6B-E 128M bits DDR SDRAM
EDD1216AJTA-7A-E 128M bits DDR SDRAM
EDD1216AJTA-7B-E 128M bits DDR SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDD1216AJTA-5C-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216AJTA-6B-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216AJTA-7A-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216AJTA-7B-E 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128M bits DDR SDRAM
EDD1216ALTA 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)
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