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參數(shù)資料
| 型號： | EDD1216AATA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 128M bits DDR SDRAM (8M words x 16 bits) |
| 中文描述： | 128兆位DDR SDRAM內(nèi)存（800萬字× 16位） |
| 文件頁數(shù)： | 26/49頁 |
| 文件大?。?/td> | 569K |
| 代理商： | EDD1216AATA |
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EDD1216AATA
Data Sheet E0444E40 (Ver. 4.0)
26
Auto Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2)
cycle after READA command input.
tRAP specification for READA allows a read command with auto precharge to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column
command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge
command does not limit row commands execution for other bank. Refer to ‘Function truth table and related
note(Notes.*14).
out0
out1
out2
out3
CK
/CK
DQ
Command
tRP (min)
tRAP (min) = tRCD (min)
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
NOP
2 cycles (= BL/2)
READA
ACT
DQS
tAC,tDQSCK
tRPD
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the
next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row
commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge
Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14)‘.
in1
in2
in3
in4
CK
/CK
DQ
Command
DM
tRAS (min)
tRCD (min)
tRP
DQS
ACT
WRITA
ACT
BL/2 + 3 cycles
Note: Internal auto-precharge starts at the timing indicated by " ".
BL = 4
NOP
NOP
Burst Write (BL = 4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD1216AATA-5 | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5B-E | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5C-E | 128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-7A-E | 128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-7B-E | 128M bits DDR SDRAM (8M words x 16 bits) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD1216AATA-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits, DDR400) |
| EDD1216AATA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
| EDD1216AATA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits DDR SDRAM (8M words x 16 bits) |
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