參數(shù)資料
型號: EBJ41UF8BAS0-GN-F
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 1G X 64 DDR DRAM MODULE, ZMA204
封裝: HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204
文件頁數(shù): 21/21頁
文件大小: 204K
代理商: EBJ41UF8BAS0-GN-F
EBJ41UF8BAS0
Preliminary Data Sheet E1545E20 (Ver. 2.0)
9
SPD for Intel Extreme Memory Profile (EBJ41UF8BAS0-GN)
Byte No. Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
176
Intel extreme memory profile ID string
0
00H
TBD
177
Intel extreme memory profile ID string
0
00H
TBD
178
Intel extreme memory profile
organization type
0
00H
TBD
179
Intel extreme memory profile revision
0
00H
TBD
180
Medium timebase (MTB) dividend
for profile 1
0
00H
TBD
181
Medium timebase (MTB) divisor
for profile 1
0
00H
TBD
182
Medium timebase (MTB) dividend
for profile 2
0
00H
TBD
183
Medium timebase (MTB) divisor
for profile 2
0
00H
TBD
184
Reserved for global byte
0
00H
TBD
[For Profile 1]
Byte No. Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
185
Module VDD voltage level
0
00H
TBD
186
SDRAM minimum cycle time
(tCK (min.))
0
00H
TBD
187
SDRAM minimum /CAS latencies time
(tAA (min.))
0
00H
TBD
188
SDRAM /CAS latencies supported, LSB
(CL MASK)
0
00H
TBD
189
SDRAM /CAS latencies supported, MSB
(CL MASK)
0
00H
TBD
190
Minimum CAS write latency time
(tCWL(min))
0
00H
TBD
191
SDRAM minimum row precharge time
(tRP)
0
00H
TBD
192
SDRAM minimum /RAS to /CAS delay
(tRCD)
0
00H
TBD
193
SDRAM write recovery time (tWR (min))
0
00H
TBD
194
SDRAM upper nibbles for tRAS and tRC
0
00H
TBD
195
SDRAM minimum active to precharge
time (tRAS), LSB
0
00H
TBD
196
SDRAM minimum active to active /auto-
refresh time (tRC), LSB
0
00H
TBD
197
Maximum average periodic refresh interval
(tREFI), LSB
0
00H
TBD
198
Maximum average periodic refresh interval
(tREFI), MSB
0
00H
TBD
199
SDRAM minimum refresh recovery time
delay (tRFC), LSB
0
00H
TBD
200
SDRAM minimum refresh recovery time
delay (tRFC), MSB
0
00H
TBD
201
SDRAM minimum internal read to
precharge command delay (tRTP)
0
00H
TBD
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