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參數(shù)資料
| 型號： | EBJ41UF8BAS0-GN-F |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 1G X 64 DDR DRAM MODULE, ZMA204 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 204K |
| 代理商： | EBJ41UF8BAS0-GN-F |
EBJ41UF8BAS0
Preliminary Data Sheet E1545E20 (Ver. 2.0)
18
CKE (input pin)
CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers.
Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the
power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read
and write accesses.
Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down.
Input
buffers, excluding CKE, are disabled during self-refresh.
DQ (input and output pins)
Bi-directional data bus.
DQS and /DQS (input and output pin)
Output with read data, input with write data. Edge-aligned with read data, centered in write data.
The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during
READs and WRITEs.
ODT (input pins)
ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only
applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to
disable ODT.
DM (input pins)
DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS.
VDD (power supply pins)
1.5V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
3.3V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
VTT (power supply pin)
I/O termination supply for SDRAM.
VREFDQ (power supply)
Reference voltage for DQ.
VREFCA (power supply)
Reference voltage for CA.
/RESET (input pin)
/RESET is negative active signal (active low) and is referred to GND.
Detailed Operation Part, Electrical Characteristics and Timing Waveforms
Refer to the EDJ2104BASE, EDJ2108BASE datasheet (E1505E).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EC11.0001.001 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.201 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.301 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.401 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0021.001 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBJ41UF8BCF0 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCF0-DJ-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCF0-GN-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCS0 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB DDR3 SDRAM SO-DIMM |
| EBJ41UF8BCS0-DJ-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB DDR3 SDRAM SO-DIMM |
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