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參數(shù)資料
| 型號(hào)： | EBE41FE4ACFT-6E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁(yè)數(shù)： | 5/22頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | EBE41FE4ACFT-6E-E |
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EBE41FE4ACFT
Data Sheet E1091E30 (Ver. 3.0)
13
13. Measured from
150mV to + 150mV on the differential waveform. The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the
differential 0V crossing.
14. Edge rate matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is
measured using a ± 75mV window centered on the median cross point where REFCLK+ rising meets
REFCLK- falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope uses
for the edge rate calculations. The rising edge rate of REFCLK+ should be compared to the falling edge
rate of REFCLK-. The maximum allowed difference should not exceed 20% of the slowest edge
15. Tstable is the time the differential clock must maintain a minimum ±150mV differential voltage after rising
/falling edges before it is allowed to droop back into the ±100mV differential range.
16.Measured with a single-ended input voltage of 1V.
17. Applies to RefClk and RefClk#.
18. This parameter is not a direct clock output parameter but it indirectly determines the clock output
parameter TREF-JITTER.
19. The net transport delay is the difference in time of flight between associated data and clock paths. The
data path is defined from the reference clock source, through the TX, to data arrival at the data sampling
point in the RX. The clock path is defined from the reference clock source to clock arrival at the same
sampling point. The path delays are caused by copper trace routes, on-chip routing, on-chip buffering,
etc. They include the time-of-flight of interpolators or other clock adjustment mechanisms. They do not
include the phase delays caused by finite PLL loop bandwidth because these delays are modeled by the
PLL transfer functions.
20. Direct measurement of phase jitter records over NSAMPLE periods may be impractical. It is expected that
the jitter will be measured over a smaller, yet statistically significant, sample size and the total jitter at
NSAMPLE samples extrapolated from an estimate of the sigma of the random jitter components.
21. Measured with SSC enabled on reference clock generator.
22. As “measured” after the phase jitter filter. This number is separate from the receiver jitter budget that is
defined by the TRX-Total-MIN parameters.
23. This maximum value is below the noise floor of some test equipment.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EBE41FE4ACWR | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Fully Buffered DIMM |
| EBE41FE4ACWR-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Fully Buffered DIMM |
| EBE41FE4ACWT | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Fully Buffered DIMM |
| EBE41FE4ACWT-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Fully Buffered DIMM |
| EBE41RE4AAHA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks) |
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