參數(shù)資料
型號: EBE41FE4ACFT-6E-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M X 72 DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, FBDIMM-240
文件頁數(shù): 3/22頁
文件大?。?/td> 205K
代理商: EBE41FE4ACFT-6E-E
EBE41FE4ACFT
Data Sheet E1091E30 (Ver. 3.0)
11
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
Symbol
min.
typ.
max.
Units
Note
EI Assertion pass-thru timing
tEI
propagate
4
clks
EI deassertion pass-thru timing
tEID
bit lock
clks
EI assertion duration
tEI
100
clks
Resample pass-thru time
1.075
ns
Resynch pass-thru time
2.075
ns
Bit lock Interval
tBitLock
119
frames
Frame lock Interval
tFrameLock
154
frames
Note: 1. The EI stands for
″Electrical Idle″.
Power Specification Parameter and Test Conditions
-6E
Frequency (Mbps)
667
Parameter
Symbol
Power Supply max.
Unit
Conditions
Note
@1.5V
2.60
A
@1.8V
2.43
A
Idle Current,
single or last
DIMM
Idd_Idle_0
Total
7.85
W
L0 state, idle (0 BW)
Primary channel enabled,
Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V
3.40
A
@1.8V
2.41
A
Idle Current, first
DIMM
Idd_Idle_1
Total
9.08
W
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V
3.90
A
@1.8V
4.56
A
Active Power
Idd_Active_1
Total
13.94
W
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
@1.5V
3.70
A
@1.8V
2.08
A
Active Power,
data pass through
Idd_Active_2
Total
8.92
W
L0 state
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
@1.5V
4.00
A
@1.8V
2.18
A
Training
Idd_Training
(for AMB spec.
Not in SPD)
Total
9.59
W
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
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