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參數(shù)資料
| 型號： | EBD52UC8AKFA-5B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | JT 26C 26#20 SKT GRND PLUG |
| 中文描述： | 64M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | EBD52UC8AKFA-5B-E |
EBD52UC8AKFA-5-E
Preliminary Data Sheet E0601E10 (Ver. 1.0)
5
Serial PD Matrix
Byte No.
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
0
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
1
0
0
0
0
0
0
0
80H
128 bytes
1
0
0
0
0
1
0
0
0
08H
256 bytes
2
Memory type
0
0
0
0
0
1
1
1
07H
DDR SDRAM
3
Number of row address
0
0
0
0
1
1
0
1
0DH
13
4
Number of column address
0
0
0
0
1
0
1
0
0AH
10
5
Number of DIMM ranks
0
0
0
0
0
0
1
0
02H
2
6
Module data width
0
1
0
0
0
0
0
0
40H
64
7
Module data width continuation
0
0
0
0
0
0
0
0
00H
0
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04H
SSTL2
9
DDR SDRAM cycle time, CL = 3
0
1
0
1
0
0
0
0
50H
5.0ns
*1
10
SDRAM access from clock (tAC)
0
1
1
1
0
0
0
0
70H
0.7ns
*1
11
DIMM configuration type
0
0
0
0
0
0
0
0
00H
None.
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8
μ
s
13
Primary SDRAM width
0
0
0
0
1
0
0
0
08H
×
8
14
Error checking SDRAM width
0
0
0
0
0
0
0
0
00H
None.
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
0
1
01H
1 CLK
16
0
0
0
0
1
1
1
0
0EH
2, 4, 8
17
0
0
0
0
0
1
0
0
04H
4
18
0
0
0
1
1
1
0
0
1CH
2, 2.5, 3
19
0
0
0
0
0
0
0
1
01H
0
20
0
0
0
0
0
0
1
0
02H
1
21
SDRAM module attributes
0
0
1
0
0
0
0
0
20H
Differential
Clock
22
SDRAM device attributes: General
1
1
0
0
0
0
0
0
C0H
VDD ± 0.2V
23
Minimum clock cycle time at CL = 2.5
0
1
1
0
0
0
0
0
60H
6.0ns
*1
24
Maximum data access time (tAC) from
clock at CL = 2.5
0
1
1
1
0
0
0
0
70H
0.7ns
*1
25
Minimum clock cycle time at CL = 2
0
1
1
1
0
1
0
1
75H
0.75ns
*1
26
Maximum data access time (tAC) from
clock at CL = 2
Minimum row precharge time (tRP)
-5B
0
1
1
1
0
1
0
1
75H
0.75ns
*1
27
0
0
1
1
1
1
0
0
3CH
15ns
-5C
0
1
0
0
1
0
0
0
48H
18ns
28
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
-5B
-5C
0
0
1
0
1
0
0
0
28H
10ns
29
0
0
1
1
1
1
0
0
3CH
15ns
0
1
0
0
1
0
0
0
48H
18ns
30
Minimum active to precharge time
(tRAS)
0
0
1
0
1
0
0
0
28H
40ns
31
Module rank density
0
1
0
0
0
0
0
0
40H
256M bytes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD52UC8AKFA-5C | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AMFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UC8AMFA-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
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