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參數(shù)資料
| 型號(hào)： | EBD52UC8AKFA-5B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | JT 26C 26#20 SKT GRND PLUG |
| 中文描述： | 64M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 190K |
| 代理商： | EBD52UC8AKFA-5B-E |
EBD52UC8AKFA-5-E
Preliminary Data Sheet E0601E10 (Ver. 1.0)
12
Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)
Parameter
Symbol
Pins
max.
Unit
Note
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/CS, CKE
90
pF
Input capacitance
CI2
CK, /CK
60
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
15
pF
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
(DDR SDRAM Component Specification)
-5B
-5C
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Clock cycle time
tCK
5
8
5
8
ns
10
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from CK, /CK
tAC
–0.7
0.7
–0.7
0.7
ns
2, 11
DQS output access time from CK, /CK
tDQSCK
–0.55
0.55
–0.55
0.55
ns
2, 11
DQS to DQ skew
tDQSQ
—
0.4
—
0.4
ns
3
DQ/DQS output hold time from DQS
tQH
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.5
—
0.5
ns
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time
from CK, /CK
Read preamble
tHZ
—
0.7
—
0.7
ns
5, 11
tLZ
–0.7
0.7
–0.7
0.7
ns
6, 11
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.4
—
0.4
—
ns
8
DQ and DM input hold time
tDH
0.4
—
0.4
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
9
Write command to first DQS latching
transition
tDQSS
0.72
1.28
0.72
1.28
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
tCK
Address and control input setup time
tIS
0.6
—
0.6
—
ns
8
Address and control input hold time
tIH
0.6
—
0.6
—
ns
8
Address and control input pulse width
tIPW
2.2
—
2.2
—
ns
7
Mode register set command cycle time
tMRD
2
—
2
—
tCK
Active to Precharge command period
tRAS
40
120000
40
120000
ns
Active to Active/Auto refresh command
period
tRC
55
—
60
—
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD52UC8AKFA-5C | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AKFA-5-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks) |
| EBD52UC8AMFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UC8AMFA-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
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