
 602
SAM4CP [DATASHEET]
43051E–ATPL–08/14
32.6.7 PIO Input Filter Enable Register
Name:
PIO_IFER
Address:
0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x4800C020 (PIOC)
Access:
Write-only 
This register can only be written if the WPEN bit is cleared in 
“PIO Write Protection Mode Register” 
.
 P0-P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
31
P31
30
P30
29
P29
28
P28
27
P27
26
P26
25
P25
24
P24
23
P23
22
P22
21
P21
20
P20
19
P19
18
P18
17
P17
16
P16
15
P15
14
P14
13
P13
12
P12
11
P11
10
P10
9
8
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0