
 105
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See 
“Flexible Second Operand”
 for details of the options.
imm12
is any value in the range 0-4095.
Operation
The ADD instruction adds the value of 
Operand2
 or 
imm12
 to the value in 
Rn
.
The ADC instruction adds the values in 
Rn
 and 
Operand2
, together with the carry flag.
The SUB instruction subtracts the value of 
Operand2
 or 
imm12
 from the value in 
Rn
.
The SBC instruction subtracts the value of 
Operand2
 from the value in 
Rn
. If the carry flag is clear, the result is reduced
by one.
The RSB instruction subtracts the value in 
Rn
 from the value of 
Operand2
. This is useful because of the wide range of
options for 
Operand2
.
Use ADC and SBC to synthesize multiword arithmetic, see 
Multiword arithmetic examples
 on.
See also 
“ADR”
.
Note:
ADDW is equivalent to the ADD syntax that uses the 
imm12
 operand. SUBW is equivalent to the SUB syntax
that uses the 
imm12
 operand.
Restrictions
In these instructions:
Operand2
 must not be SP and must not be PC.
Rd
 can be SP only in ADD and SUB, and only with the additional restrictions:
Rn
 must also be SP.
Any shift in 
Operand2
 must be limited to a maximum of 3 bits using LSL.
Rn
 can be SP only in ADD and SUB.
Rd
 can be PC only in the ADD{
cond
} PC, PC, Rm instruction where:
The user must not specify the S suffix.
Rm
 must not be PC and must not be SP.
If the instruction is conditional, it must be the last instruction in the IT block.
With the exception of the ADD{
cond
} PC, PC, Rm instruction, 
Rn
 can be PC only in ADD and SUB, and only with
the additional restrictions:
The user must not specify the S suffix.
The second operand must be a constant in the range 0 to 4095.
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before
performing the calculation, making the base address for the calculation word-aligned.
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with 
Rn
 equal to the PC,
because the assembler automatically calculates the correct constant for the ADR instruction. 
When 
Rd
 is PC in the ADD{
cond
} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored.
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If 
S
 is specified, these instructions update the N, Z, C and V flags according to the result.