
781
SAM4CP [DATASHEET]
43051E–ATPL–08/14
36.7.7 USART Interrupt Disable Register
Name:
US_IDR
Address:
0x4002400C (0), 0x4002800C (1), 0x4002C00C (2), 0x4003000C (3), 0x4003400C (4)
Access:
Write-only
For SPI specific configuration, see
“USART Interrupt Disable Register (SPI_MODE)” on page 782
.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
RXRDY: RXRDY Interrupt Disable
TXRDY: TXRDY Interrupt Disable
RXBRK: Receiver Break Interrupt Disable
ENDRX: End of Receive Buffer Interrupt Disable (available in all USART modes of operation)
ENDTX: End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
OVRE: Overrun Error Interrupt Enable
FRAME: Framing Error Interrupt Disable
PARE: Parity Error Interrupt Disable
TIMEOUT: Time-out Interrupt Disable
TXEMPTY: TXEMPTY Interrupt Disable
ITER: Max Number of Repetitions Reached Interrupt Disable
TXBUFE: Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
RXBUFF: Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
NACK: Non Acknowledge Interrupt Disable
CTSIC: Clear to Send Input Change Interrupt Disable
MANE: Manchester Error Interrupt Disable
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANE
23
–
22
–
21
–
20
–
19
18
–
17
–
16
–
CTSIC
15
–
14
–
13
12
11
10
9
8
NACK
RXBUFF
TXBUFE
ITER
TXEMPTY
TIMEOUT
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
RXBRK
TXRDY
RXRDY